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| xr-t7295e ...the analog plus company tm ! !!" # $! !" %&!" ' ' (# % ' (## ) ( features %*++) , ,! -+ .*+/! 0 !+ 1& !) ! (!,(-+ ! (!,(!2 +& 3 + * - ) !!+ '3 4!5 -* +) !& + 56 7#" 7##' 7 - ,! applications , ! 85!2 -9:;-9 .* & 4 1 .* & % 0 1&+ *+ +< general description 16 (1# ' ,*++) , 6 & !+ + & ! !<+ + 16 * 56 6 (1# 1 & - figure 10 16 ! 6 ,*! !, .*+/! ! !+ " *!&( !!+ 7 " +!2(!) &" +! (!,( + +! (!,(,.*)( +!2 ! 16 + ) & , *+(+" 56 ! * !+ + + ! !* * + 16 !(6 .*+/ ,! + +! !, ! ' = 16 * 6 + * ) !!+" ! 6 ,, ) >6 * ) ++!5 ,! , &!* !, ,+ +! ! ,! * 56 * + 6 &!! ++ figure 1 6!5 6 +!2 & !, 6 16 (1# ' &*,* ) * + 0- 6!+!) 16 (1# ' + + 6 ( + ; 4 ! ( + -0? 2 ,! *, &!* !& + ! + + ,! ;- ! -1-( +! 4+ , ! 6 (1# ' 6 ordering information part no. package operating temperature range (1# '( 4 + 4; 4 ( ! @' (1# '( a ? + ?; -0? ( ! @' xr-t7295e block diagram figure 1. block diagram *! 7 42 ;! -+ 46 ; !! %+ 3 0 ;+ +! 0- %.*) 46 .* ! * .*+/ 1* 2 +! 0- 7 b 8 ' ' # # c= 0-1> 1 1 1 $ 0 0- 8; 1 4; 1 $ 4% 4% 3 ;; 78; 3 ;; ;78;;3 ;; 78; & ! ;! .*+/ xr-t7295e pin configuration ' # ' # 3 ;; 0-1> c= 1 78; 8 1 4% 4; 1 8; 1 $ $ 4% 1 0- 0 3 ;; 78;; 3 ;; ; 78; 20 lead soj (jedec, 0.300?) ' # # ' 3 ;; 0-1> c= 1 4; 1 8; 1 $ $ 78; 8 1 4% 4% 1 0- 0 3 ;; 78;; 3 ;; ; 78; 20 lead pdip (0.300?) pin description pin # symbol type description 78; analog ground. 8 receive input. 9 + +! * " 1 (1 test mode control 1 and 2. + &! + 56 6 ) * 1 1 9 &* 6 ! 6 !* + "' 4%(4% pll filter 1 and 2. <+ ! % d ! 5 6 - figure 3 # 0- 0 receive loss-of-signal. 16 66 ! +! !, + 6 * 0 0 receive pll loss-of-lock. 16 66 ! +! !, 4 ,.*) +!2 78;; digital ground for pll clock. 7!* + ,! ++ *) * )6!!* +) 56 4 +!2 78; digital ground for exclk. 7!* + ,! ++ *) * )6!!* +) 56 $ 3 ;; ; 5v digital supply ( 10%) for pll clock. 4!5 ,! ++ *) * )6!!* +) 56 4 +!2 3 ;; 5v digital supply ( 10%) for exclk. 4!5 ,! ++ *) * )6!!* +) 56 $ $ external reference clock. + >/ & +!2 &* ! 6 * 16 *) )+ !, $" , ! 3 ;; : ++ " &* d(d $ 0 receive clock. ! +!2 + ! 6 &+ .* & ' 8; 1 0 receive negative data. 8 *+ !* * ! 6 &+ .* & 4; 1 0 receive positive data. 4! *+ !* * ! 6 &+ .* & # 1 output in-circuit test control (active-low). , 1 ,! +!5" ++ + !* * $" 4; 1 " 8; 1 " 0-" 0 + 66( & ! ++!5 ,! (* c= receive equalization bypass. 66 ! 6 ) 6 + .*+/ +!5 + 6 .*+/ 6 6 0-1> loss-of-signal threshold control. 16 !+ ,! ! 6 !!+ 6 * +! (!,( + 6 6!+ 16 ! ) ,! 78;" 3 ;; : " ! 3 ;; 0-1> 3 ;; 5 v analog supply ( 10%). xr-t7295e dc electrical characteristics test conditions: -40 c ta +85 c, v dd =5v 10% typical values are for v dd =5.0v,25 c, and random data. maximum values for v dd =5.5vat85 c all 1s data. symbol parameter min. typ. max. unit conditions electrical characteristics ;; 4!5 -* +) * c=e c=e # & & logical interface characteristics 3 3 > * 3!+ !5 >6 78;; 3 ;; ; (' ' 3 ;; ; 3 3 3 0 3 0> 0* * 3!+ !5 >6 78;; 3 ;; ; (' 3 ;; ; 3 3 ('& '& * % ! % * 2 ( (' ' (' & (' ! 3 ;; @'3 ++ * < # 3 # 3 ;; 78; specifications are subject to change without notice absolute maximum ratings 4!5 -* +) ('3 ! @'3 -! 1& * ( ! @ ' 3!+ ) 4 ('3 ! 3 ;; @'3 4!5 ; ! #&a <&*& ++!5 + 3!+ 8 56 ! 78; ('3 ! @'3 xr-t7295e ' (1# 1 & -) & (1# ' -) & = figure 2. application diagram (1# ' (1# 1 & !<+ + #' = ( '= system description receive path configurations 16 & figure 2 6!5 ) + ) & +! ,! 6 (1# ' 6 + 6 figure 1 " 6 + .*+/ +* ) c=e ! ) ) c=e 16 .*+/ ) ! ! ++!5 ) , !, 6 (1# ' ! ) & +) ! <+ .*+/ figure 3 ++* 6 6 ! ! ,! 5! " 6 + ,!& 6 !<+ + , +) ! 6 8 * 6 &!" 6 * 6!*+ c=e " 6 .*+/ 6 6 , 6 + +! 6 = , 6 + +! + 6 =" 6 .*+/ ) ) c=e " <+ + .*+/ 5!2 6 (1# ' 6 &!" 6 + 8 +) .*+/" 6 !(6 .*+/ 6!*+ ) ) c= e !6 " 6 + 8 &* & 6 & +* +& table 1 16 !&& &! + ! 6!5 figure 3 16 #' ! & 6 !<+ + 56 6 & figure 3 " , 6 ,< .*+/ +* 6 + &!" 6 #' ! ! .* 16 + !* + 6!*6 6 % ! ! 8 16 ; 8 ++) 16 * 6 8 ) ++) % -0? 2 % ; 4 2 pulse mask at the 34.368 mbps interface table 2 6!5 6 *+ ,! 6 & !* * ! figure 4 6!5 6 *+ & 2 .*& ,! !&& 7# reqb losthr minimum signal unit 3 reqb losthr soj 2 dip unit 3 ' &3 2 3 ;; : ' &3 2 3 ;; &3 2 ' &3 2 3 ;; : ' &3 2 3 ;; ' &3 2 notes 1 maximum input amplitude under all conditions is 1.1 vpk 2 the soj device performance is enhanced by decreased package parasitics. 3 although system designers typically use power in dbm to describe input levels, the xr-t7295e responds to peak input signal amplitude. therefore, the xr-t7295e input signal limits are given in mv pk. table 1. receive input signal amplitude requirements? xr-t7295e line termination and input capacitance 16 !&& &! 6!5 figure 3 16 #' ! & 6 !<+ + 56 6 & 16 % ! ! 8 !* + 6 + ! 6 * 56!* * 6 ++) ; ++ ! 8 16 * 6 8 % -0? 2 % ; 4 2 external loop filter capacitor figure 3 6!5 6 !! ! <+ % ! 6 4%:4% 16 ! !, 6 4 ,+ !( !+/" +!5(+2 ! 6!*+ * & ! 56 6 +* % d + < 0,,(6 85!2 (' , - f ; - ' , =0 +! ,! #' % % 8 c= 4% 4% xr-t7295 - f (' , 8 xr-t7295 c= ; - % #' % 4% 4% %< .*+/ figure 3. receiver configuration 'g' , !, + timing recovery output jitter 16 !+ h ! 6 $ !* * * !&+ ! ! ! !, 5! !& ! % " !& h ! $ * !, h ! 6 !& + 16 < ! * 6 h , 6 " 566 6 +! 6 5 * !* * h -!" ! !* 56 6 (1# ' ! ! !* 6 !* + ! 6 6!*6 6 !5 * + xr-t7295e # h ! $ 16 &* !, 6 ++) h ,*! !, 6 4 56" 566 * ,*! !, 6 * ) %! 66 " 6 &!* !, h 7 h + ! ! 6 .*+) !, 6 !5 * +) ) 5!2 * figure 8 6!5 6 * ) 5!2" table 3 + 6 ) + h ,!& 6 + 56 6 5!2 '' @ '' 11( ' '' ( ' ' 3 # '' @ ' ' '' ( ' '' ' '' @ ' 8!&+ *+ figure 4. pulse mask at the 34.368 mbit/s interface parameter value 4*+ -6 8!&++) *+ ++ &2 !, + + &* !,!& 56 6 & 2 figure 4 " !, 6 4 6 ;! 0 !<+ 4 1 ! & #' 8!&+ 42 3!+ !, 2 4*+ 3 42 3!+ !, - 8! 4*+ 3 3 8!&+ 4*+ a6 '' ! !, 6 & +* !, 4! 8 4*+ 6 !, 4*+ + ' ! ' ! !, 6 a6 !, 4! 8 4*+ 6 8!&+ >+, & +* ' ! ' table 2. e3 pulse specification at the transmitter output port xr-t7295e jitter transfer characteristic 16 h , 6 6 ,! !, * h 6 6 6 $ !* * ,*! !, * h ,.*) table 3 6!5 & ! h , 6 & figure 6 + ! 6!5 ) + 6 " 56 6 ! !! table 3 +6!*6 !*& ! ! ,) h , 6 .*& " 6 (1# ' ,!&! ! 6 ! +*! !, 6 parameter typ. max. unit 7 ? ++ 2 ( ! ( 2 ++( ' 2 ( ! ( 2 2(!( 2 ? 1 , 6 6 42 ' = , = ' ' = 2>/ notes 1 repetitive input data pattern at nominal e3 level with v dd =5v ta = 25 c. 2 repetitive 1000 input at nominal e3 level with v dd =5v,ta = 25 c. table 3. generated jitter and jitter transfer characteristics jitter accommodation 9 ++ ++!5 + ! !! " 6 h !&&!! !, 6 (1# ' < 6 +& ,! !(, ! ! = i ( 16 ) + 3 ;; e'3"1e ' " !&+ + ++ h !&&!! !, 6 6!5 figure 6 (' ( ( ( ( ' $ '$ $ '$ $ '$ 4 $ e '= ,= e ' 2>/ frequency (hz) figure 5. typical pll jitter transfer characteristics magnitude response (db) figure 6. lower limit of maximum tolerable input jitter at 34.368 mbit/s ' ' 2 2 2 '2 2 2 2 2 ' 4 '' # g 4=- 11 7 -$ peaktopeak jitter amplitude (ui) jitter frequency (hz) xr-t7295e false-lock immunity %+ (+!2 , 6 !! 56 4 ! +!2 ! + 6 (+!2 ,.*) ! .*+ ! 6 !& 16 (1# ' * !& ! ,.*): 6 (+!2 6* ! ,+ (+!2 !(6 ,.*) !& ! !*!* +) !& 6 $ , ! 6 4 +!2 , 6 ,.*) ,, 5 6 $ 4 +!2 < !<&+) 'd !, $" !! *) ! ,! (.* ! !, 6 ! ,.*) 6 acquisition time , + * + *& ! +) 8 " 6 &<&*& & 5 6 +! !, !5 !(, ! ! & , !5 6 +) +" 6 + 5 6 +! !, + !(, ! ! & loss-of-lock indication !" 6 4 .* ! *) &!! 6 4 +!2 ,.*) + ! 6 $ ,.*) 16 .* ! * + ! &!! 6 *& ! ! + 6 (+!2 566 !* !, !&+ 6 +& 16 0 +& , 6 ! !6 !, 6 ,!++!5 !! < f ( 16 ,, 5 6 4 +!2 6 $ %.*) < !<&+) 'd ( 16 & !* !, !&+ 6 +& 66 0 !* * 6 6 .* ! * 5!2 ! 6 4 ! ! ,.*) +!2 0 & 66 *+ ,.*) +!2 6 !*j 6!5" 6 &&*& 0 *+ 56 +!2 )+ data rate reqb losthr threshold unit rate reqb losthr min. max. unit &3 2 3 ;; : ' &3 2 3 ;; ' &3 2 ' #' &3 2 3 ;; : ' &3 2 3 ;; # &3 2 notes the rlos alarm is an indication of the presence of an input signal, not a bit error rate indication. table 1 gives the minimum input amplitude needed for error-free operation (ber<1e -9 ). independent of the rlos state, the device will attempt to recover correct timing and data. the rlos low-to-high transition typically occurs 1db below the high-to-low transition. table 4. analog loss-of-signal thresholds loss-of-signal detection figure 1 6!5 6 +! + &6! !, +! (!,( + 0- ! !& ! 6 0- +& !* * 0- , 6 6 +! ! + ! *) 0- 6 !* analog detection 16 +! 0- ! &!! 6 2 * + & +* 0- &2 66(!(+!5 ! * + 56 6 * + & +* < 6 +! (!, + 6 6!+ , table 4 16 0- +!5(!(66 ! * + +! !* ++ ) ++) = +!5 6 66(!(+!5 ! ++ 16 6) 0- 6 0 " 6 0- +& & 66 ,! + +!2 )+ " ++!5 ,! ) & ! !, 0- !! 56!* 6 * !, <+ +& +6 1! ++!5 ,! ) ++ !, ! ! +2 ,, +! " 6 +! (!,( + 6 6!+ + + * 6 0-1> - 0-1> e 3 ;; ! 6 +!5 +! (!,( + 6 6!+j 0-1> e 3 ;; : !* * 5! '2 d ! !+ 5 3 ;; ; 78;; ! & 6 6!+ 0-1> e 78; ! 6 66 6 6!+ 16 0-1> &* ! +* !5 * &* ! 6 * ! ! xr-t7295e 4=- ( 4=- ( *! + 0 3!+ 4!! (1# ' ! !! , ! = # 2>/ = &< @ ;! figure 7. test set-up for interference immunity requirements digital detection ! ! 6 + & +* &!! !, 6 +! 0- !" 6 + 0- ! &!! 6 ! ) 16 0- +& ! 66 , ! &! ! * !* 6 & 16 +& ! +!5 56 + 6 !* !, ! * 16 6) &&/ 0- 6 * &&*& 0- *+ 56 !, +!2 )+ note rlos chatter can still occur. when reqb = 1, input signal levels above the analog los threshold can still be low enough to result in a high bit error rate. the resultant data stream (containing errors) can temporarily activate the digital los detector, and rlos chatter can occur. therefore, rlos should not be used as a bit error rate monitor. rlos chatter can also occur when rlol is activated (high). phase hits ! ! 6 6 6 * " 6 (1# ' * ! !(, ! ! + 6 & ;* 6 .* ! &" 0- &) & !+) recovered clock and data timing table 6 figure 9 *&&/ 6 & +! 6 5 6 66( +! + $" 4; 1 " 8; 1 ++ *) )+ & +! 6 , ! 3 ;; : 6 6!+ ++ 4; 1 8; 1 6 ! 6 !, $ + * 6 ,++ !, $ ! *+ 8 66 ++ ! 4; 1 +!5 ++ ! 8; 1 *+ 66 ++ ! 8; 1 +!5 ++ ! 4; 1 " /! !* +!5 ++ ! !6 4; 1 8; 1 parameter min. typ. max. unit *! ( ( = table 5. interference requirement interference immunity 16 (1# ' !& + 56 6 , + 6 figure 7 table 5 16 5! ! !( )6!!* in-circuit test capability a6 *++ +!5" 6 1 ,! ++ + !* * *,, $" 4; 1 " 8; 1 " 0-" 0 ! + 66 !* * & 16 ,* ++!5 (* ! ! ! 6 ! 56!* ! ,! (1# ' *,, & a6 ,! 66" 6 1 ! ! ,, ! ! + *++(* !&++) ' 2 ! ! 6 j 6,!" * + 6 ! ,! !&+ ! ! 16 6 !+) ,! 566 + *++(* : *++(!5 ! board layout considerations power supply bypassing figure 8 ++* 6 !&& !5 * +) ) 5!2 % ! ) 6 + * + 16 +! * +) 3 ;; ) ) * % ! 6+ 6 &! , &!* !, 66(,.*) ! ) 6 ) & ) 6 +! 7!! .*+)" 66(,.*) +!5 + * ! 6!*+ * %++)" &! & ! 6 ++ !* !! & ! +!5(& !* + xr-t7295e % - 8! -6+ = @'3 % 78;; 78; 78; 3 ;; ; 3 ;; xr-t7295e figure 8. recommended power supply bypassing network note recommended shield beads are the fairrite 2643000101 or the fairrite 2743019446 (surface mount). 3 ;; receive input 16 !! ! 6 * " 8 " &* ,*++) ! 8! (!* + &* &&/ +! 6 6 ,!& 6 + 6 ! ! 6 * ) ! !* + ! 6 (1# ' * +) 6 +(!(! ! !, 6 * + pll filter capacitor 16 4 ,+ ! 5 4% 4% &* + +! ! 6 6 ! + 16 4% 4% h" ++!5 ,! 6! + +6 56 ! ! ! ! 6 <+ ! 8! (!* + ! 6 4% 4% &) 4 ,!& handling precautions +6!*6 !! *) 6 ! 6 " ! *! 6!*+ 2 ! ! < ! * ! +! 6 -; * 6+ &!* compliance specifications !& + 56 ccitt recommendations g.703, g.775 and g.824 " xr-t7295e timing characteristics test conditions: all timing characteristics are measured with 10pf loading, -40 c ta +85 c, v dd =5v 10% symbol parameter min. typ. max. unit > > +!2 1& d( d ' +!2 %++ 1& d( d ' ;3 ; -(9 1& '' ; ; >!+ 1& ' >;3 4! ! ;+) # +!2 ;*) )+ ' ' '' d note 1 the total delay from r in to the digital outputs rpdata and rndata is three rclk clocks. table 6. system interface timing characteristics (see figure 9) figure 9. timing diagram for system interface $ 4; 1 0 8; 1 ; >;3 > > ; ;3 xr-t7295e ' '# $ 3 3 0 - 1 > ' # $ ' - -a ; 4( 0- 14 0 14 receiver monitor outputs 0 0- # 8 $ 3 ; ; 3 ; ; 3 ; ; ; 78;; 78; 78; c= 8; 1 ' 4; 1 1 1 4% 4% ' 0-1> 1: # % #' #' 8491 - 78 18 0 $ = = ' ' ' # =' 1 $ 4 78; 3 ; ; 3 ; ; ; 004 004 ;-"-1-(:: 1 0- ' 1: 1 3 ' 8 0; - ; 0; - $ 8; 1 4; 1 # ;0 =43 18; 1 1 $ 14; 1 # 78; 78;; 1 4 87 11 4 1 87 $0 # 40- 87 ' 8k u2 xr-t7296 87 $0 40- 004 004 1: 1 0- 1 3 1 8 0; - ; 0; - receiver ' # ' - -a ; 4( outputs 1 4' = 1 87 11 4 ' # # 8k = 18; 1 = 14; 1 % % % =1 % 1 = ; % 1 = ; l % 1 # % % 4 3 transmiter monitor outputs ;0 =43 % % % 1 8-%0 l 49- 87 8 87 =1 % 1 = ; ' % 4 ' 4 ' # 8 -9% 0981 3 1 u2 xr-t7295 # $ 4 c = 1 @ @ figure 10. evaluation system schematic xr-t7295e 20 lead plastic dual-in-line (300 mil pdip) rev. 1.00 d e a 1 e 1 e a l seating plane symbol min max min max inches ' ' ' # # ' ' ' = ' = # # # ; ' ' ' # # =- ' =- =- # =- = ## ' ' ' millimeters a 2 b 1 b c note: the control dimension is the inch column e b e a xr-t7295e ' symbol min max min max ' ' ' ((( ((( ' ' = ' ; ' # # # ' ' =- # =- > ' # ' # inches millimeters e 20 lead small outline j lead (300 mil jedec soj) rev. 1.00 d e h b a 1 seating plane note: the control dimension is the inch column a 2 a c r e 1 xr-t7295e 801 ! !! 6 6 ! &2 6 ! 6 !* ! 6 * +! ! ! &( ! " ,!& ! + +) ! !! *& ! ! +) ,! 6 * !, ) * ( 6" !) ! + * ) ! !6 6" &2 ! ! 6 6 * , !, ,& 6 6*+ ! 6 !+) ,! ++* ! * ! &) ) * ! * m , +! a6+ 6 ,!&! 6 * +! 6 ,*++) 62j ! ! +)" 6!5" *& ,! * ! !! ! ! !&& 6 * !, ) !, !* +, * ! +! 56 6 ,+* ! &+,*! !, 6 !* ! +) < ! * ,+* !, 6 +, * ! ) & ! ! ,+) ,, ,) ! ,, 4!* ! *6!/ ,! * *6 +! *+ ! !! " 5" * ! ,! 6f 6 2 !, h*) ! & 6 &&/j 6 * *& ++ *6 2 j !+ + +) !, ! !! .*+) ! * 6 *&( ! )6 ! !! ; 6 ) !*!" ! 56!+" 56!* 6 ! 5 ! !, ! !! !6 |
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